Verilog HDL,
SystemVerilog HVL,
UVM Methodology & Verification Lab

1. ASIC Flow, Module, declaration and Instantiation, Components of simulation, Procedural blocks, Lexical conventions.

2. Data types, Module Parameters, Operators, Primitives, Functional. representation in Verilog.

3. Arrays, Memories, System tasks, compiler Directives, Continuous and Procedural Assignments, Examples of Blocking and Non-blocking statements.

4. Race Condition, Timing Controls Sequential and Parallel Blocks, Conditional Statements, loops Statements.

5. Task, Functions, Difference between task and Function.

Verification Lab Combinational circuits

- 2x1 Multiplexer, 4x1 Multiplexer
- 4:2 Decoder
- Half Adder and Full Adder
- Priority encoder
- Sequential circuits
- D-ff
- SISO
- Counters
- Design and Verification of RAM.
- Design and Verification of FSM (1 FSM to be done by the students for final assessment)

Course Modules

Module 1: Introduction to SV & Data types SV Testbench Architecture, Verilog vs System Verilog, SV Data types: 2 state vs 4 state variables, Dynamic Arrays, Associative Arrays, and its Usage.

Module 2: SV Data Types Strings, Unions, Structures, Enumerated data Types, Events.

Module 3: SV Interfaces SV Interfaces: Interface ports, Mod ports, Clocking blocks, Virtual Interface, Program blocks.

Module 4: SV OOPs SV Class, Inheritance, this operator, super operator, shallow copy, deep copy, parameterized classes, typedef classes, polymorphism, abstract class, encapsulation, dynamic casting, scope resolution operators.

Module 5: Interprocess Communications (IPC), Randomization and Constraints IPC: Event, Mailbox, Semaphores Randomization & Constraints: Basics, specifying constraints, methods in constraints, random stability, random sequences, and random case.

Module 6: Assertions, DPI Introduction, Advantage and types of assertions, Sequence & property, writing assertion using operators & system tasks.

Module 7: Function coverage Code coverage, functional coverage, cover groups, cover points, cover bins, cross coverage, coverage options & methods.

Module 8: Introduction to UVM Limitations of SV testbench, Migrating from SV to UVM, UVM Architecture, UVM Class Hierarchy.

Module 9: UVM Phases & Reporting Mechanism UVM Phase categorization, UVM Reporting.

Module 10: Transaction Level Modeling TLM 1.0, TLM 2.0, Examples.

Module 11: Factory registration and methods UVM Field Macros, Factory registration, create method, factory override.

Module 12: UVCs Development UVM config database, construction of UVC, sequence generation, Sequences, Virtual Sequencer, Virtual Sequences.